Carrier Mobility in Field-Effect Transistors

Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the <100> and <110> directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer.